TMS570LS0332PZ datasheet(30/110 Pages) TI1

30 / 110 page

TMS570LS0432, TMS570LS0332

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

www.ti.com

6.3

Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset

condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the

output buffer is implemented as an open drain (drives low only). To ensure an external reset is not

arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

6.3.1

Causes of Warm Reset

Table 6-5. Causes of Warm Reset

DEVICE EVENT

SYSTEM STATUS FLAG

Power-up reset

Exception Status Register, bit 15

Oscillator fail

Global Status Register, bit 0

PLL slip

Global Status Register, bits 8 and 9

Watchdog exception / Debugger reset

Exception Status Register, bit 13

CPU Reset (driven by the CPU STC)

Exception Status Register, bit 5

Software reset

Exception Status Register, bit 4

External reset

Exception Status Register, bit 3

6.3.2

nRST Timing Requirements

Table 6-6. nRST Timing Requirements

MIN

MAX

UNIT

Valid time, nRST active after nPORRST inactive

2256tc(OSC)

(1)

tv(RST)

Valid time, nRST active (all other system reset conditions)

32tc(VCLK)

Filter time nRST pin;

tf(nRST)

Pulses less than MIN will be filtered out, pulses greater than MAX will

475

2000

generate a reset

(1)

Assumes the oscillator has started up and stabilized before nPORRST is released.

System Information and Electrical Specifications

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Product Folder Links: TMS570LS0432 TMS570LS0332

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