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TMS570LS0332PZ bảng dữ liệu(PDF) 39 Page - Texas Instruments |
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TMS570LS0332PZ bảng dữ liệu(HTML) 39 Page - Texas Instruments |
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39 / 110 page ![]() /1,2 ...1024 Phase_seg1 CAN Baud Rate DCAN1, 2 AVCLK1 VCLK Prop_seg Phase_ seg2 /1,2 ...256 SPI Baud Rate SPIx,MibSPIx /2,3 ...2 24 LIN Baud Rate LIN ADCLK MibADC /1,2 ...32 ECLK External Clock /1,2 ...65536 VCLK2 HET TU HRP /1 ...64 N2HET High Resolution Loop Clock LRP /2 0...27 VCLK2 Low Power Oscillator *The frequency at this node must not exceed the maximum HCLK frequency * FMzPLL 80 kHz 10 MHz OSCIN GCM 0 1 4 5 /1 ...64 X1 ...256 /1 ...8 /1 ...32 GCLK,GCLK2 (to CPU) HCLK (to SYSTEM) VCLK (to System and Peripheral Modules) VCLK (to N2HET) /1 ...16 /1 ...16 AVCLK1 (to DCAN1, 2) 0 1 4 5 VCLK VCLK 0 1 4 5 /1,2,4, or 8 RTICLK (to RTI+DWWD) EXTCLKIN 3 3 3 eQEP CDDISx.9 TMS570LS0432, TMS570LS0332 www.ti.com SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 6.5.2.2 Mapping of Clock Domains to Device Modules Each clock domain has a dedicated functionality as shown in the figure below. Figure 6-7. Device Clock Domains Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications 39 Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332 |
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