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TMS570LS0332PZ bảng dữ liệu(PDF) 49 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  16- and 32-Bit RISC Flash Microcontroller
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TMS570LS0332PZ bảng dữ liệu(HTML) 49 Page - Texas Instruments

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TMS570LS0432, TMS570LS0332
www.ti.com
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015
6.8.3
Master/Slave Access Privileges
The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
Table 6-18. Master / Slave Access Matrix
SLAVES ON MAIN SCR
Peripheral Control
Registers, All
Flash Module Bus2
Non-CPU Accesses
Peripheral
MASTERS
ACCESS MODE
Interface:
to Program Flash
CRC
Memories, And All
OTP, ECC, EEPROM
and CPU Data RAM
System Module
Bank
Control Registers
And Memories
CPU READ
User/Privilege
Yes
Yes
Yes
Yes
CPU WRITE
User/Privilege
No
Yes
Yes
Yes
HTU
Privilege
No
Yes
Yes
Yes
Copyright © 2012–2015, Texas Instruments Incorporated
System Information and Electrical Specifications
49
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Product Folder Links: TMS570LS0432 TMS570LS0332



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