CP3SP33SMSSLASHNOPB datasheet(331/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

TCRA

32.5.6 Reload/Capture B Register n (TCRB_n)

The TCRB_n register is a 16-bit, read/write register that holds the reload or capture value for

Timer/Counter 2. The register contents are not affected by a reset and are unknown after power-up.

TCRB

32.5.7 Timer Mode Control Register n (TMCTRL_n)

The TMCTRL_n register is a byte-wide, read/write register that sets the operating mode of the

timer/counter and the TAn and TBn pins. This register is cleared at reset. The register format is shown

below.

TEN

TAOUT

TBEN

TAEN

TBEDG

TAEDG

MDSEL

The Mode Select field sets the operating mode of the timer/counter as follows:

00 – Mode 1: PWM plus system timer.

01 – Mode 2: Dual-Input Capture plus system timer.

10 – Mode 3: Dual Timer/Counter.

11 – Mode 4: Single-Input Capture and Single Timer.

TAEDG

The TAn Edge Polarity bit selects the polarity of the edges that trigger the TAn input.

0 – TAn input is sensitive to falling edges (high to low transitions).

1 – TAn input is sensitive to rising edges (low to high transitions).

TBEDG

The TBn Edge Polarity bit selects the polarity of the edges that trigger the TBn input. In pulse-

accumulate mode, when this bit is set, the counter is enabled only when TBn is high; when

this bit is clear, the counter is enabled only when TBn is low.

0 – TBn input is sensitive to falling edges (high to low transitions).

1 – TBn input is sensitive to rising edges (low to high transitions).

TAEN

The TAn Enable bit controls whether the TAn pin is enabled to operate as a preset input or as

a PWM output, depending on the timer operating mode. In Mode 2 (Dual Input Capture), a

transition on the TAn pin presets the TCNT1_n counter to FFFFh. In the other modes, TAn

functions as a PWM output. When this bit is clear, operation of the pin for the timer/counter is

disabled.

0 – TAn input disabled.

1 – TAn input enabled.

TBEN

The TBn Enable bit controls whether the TBn pin in enabled to operate in Mode 2 (Dual In-

put Capture) or Mode 4 (Single Input Capture and Single Timer). A transition on the TBn pin

presets the corresponding timer/counter to FFFFh (TCNT1_n in Mode 2 or TCNT2_n in Mode

4). When this bit is clear, operation of the pin for the timer/counter is disabled. This bit setting

has no effect in Mode 1 or Mode 3.

0 – TBn input disabled.

1 – TBn input enabled.

TAOUT

The TAn Output Data bit indicates the current state of the TAn pin when the pin is used as a

PWM output. The hardware sets and clears this bit, but software can also read or write this bit

at any time and therefore control the state of the output pin. In case of conflict, a software

write has precedence over a hardware update. This bit setting has no effect when the TAn pin

is used as an input.

0 – TAn pin is low.

1 – TAn pin is high.

Dual Multi-Function Timers

331

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