PI7C8150BMA-33 datasheet(60/107 Pages) PERICOM

60 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 60 of 107

April 2015 – Revision 2.1

In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8150B asserts

P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the

SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8150B

also sets the received system error bit in the secondary status register.

PI7C8150B also conditionally asserts P_SERR_L for any of the following reasons:



Target abort detected during posted write transaction



Master abort detected during posted write transaction



Posted write data discarded after 2

24 (default) attempts to deliver (224 target retries

received)



Parity error reported on target bus during posted write transaction (see previous section)



Delayed write data discarded after 2

24 (default) attempts to deliver (224 target retries

received)



Delayed read data cannot be transferred from target after 2

24 (default) attempts (224

target retries received)



Master timeout on delayed transaction

The device-specific P_SERR_L status register reports the reason for the assertion of

P_SERR_L. Most of these events have additional device-specific disable bits in the

P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion

for specific events. The master timeout condition has a SERR_L enable bit for that event in

the bridge control register and therefore does not have a device-specific disable bit.

EXCLUSIVE ACCESS

This chapter describes the use of the LOCK_L signal to implement exclusive access to a

target for transactions that cross PI7C8150B.

7.1

CONCURRENT LOCKS

The primary and secondary bus lock mechanisms operate concurrently except when

a locked transaction crosses PI7C8150B. A primary master can lock a primary target

without affecting the status of the lock on the secondary bus, and vice versa. This means

that a primary master can lock a primary target at the same time that a secondary master

locks a secondary target.

7.2

ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B

For any PCI bus, before acquiring access to the LOCK_L signal and starting a series of

locked transactions, the initiator must first check that both of the following conditions are

met:



The PCI bus must be idle.



The LOCK_L signal must be de-asserted.

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