PI7C8150BMA-33 datasheet(59/107 Pages) PERICOM

59 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 59 of 107

April 2015 – Revision 2.1

S_PERR_L

Transaction Type

Direction

Bus Where Error

Was Detected

Primary/

Secondary Parity

Error Response

Bits

Delayed Write

Downstream

Secondary

x / x

Delayed Write

Upstream

Primary

1 / 1

Delayed Write

Upstream

Secondary

x / 1

X = don’t care

The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.

Table 6-7 shows assertion of P_SERR_L. This signal is set under the following conditions:



PI7C8150B has detected P_PERR_L asserted on an upstream posted write transaction

or S_PERR_L asserted on a downstream posted write transaction.



PI7C8150B did not detect the parity error as a target of the posted write transaction.



The parity error response bit on the command register and the parity error response bit

on the bridge control register must both be set.



The SERR_L enable bit must be set in the command register.

Table 6-7. Assertion of P_SERR_L for Data Parity Errors

P_SERR_L

Transaction Type

Direction

Bus Where Error

Was Detected

Primary /

Secondary Parity

Error Response

Bits

1 (de-asserted)

Read

Downstream

Primary

x / x

Read

Downstream

Secondary

x / x

Read

Upstream

Primary

x / x

Read

Upstream

Secondary

x / x

Posted Write

Downstream

Primary

x / x

2 (asserted)

Posted Write

Downstream

Secondary

1 / 1

Posted Write

Upstream

Primary

1 / 1

Posted Write

Upstream

Secondary

x / x

Delayed Write

Downstream

Primary

x / x

Delayed Write

Downstream

Secondary

x / x

Delayed Write

Upstream

Primary

x / x

Delayed Write

Upstream

Secondary

x / x

X = don’t care

The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.

The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.

6.4

SYSTEM ERROR (SERR_L) REPORTING

PI7C8150B uses the P_SERR_L signal to report conditionally a number of system error

conditions in addition to the special case parity error conditions described in Section 6.2.3.

Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the

following conditions apply:



For PI7C8150B to assert P_SERR_L for any reason, the SERR_L enable bit must be

set in the command register.



Whenever PI7C8150B asserts P_SERR_L, PI7C8150B must also set the signaled

system error bit in the status register.

15-0048

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