UPSD3312D datasheet(194/272 Pages) STMICROELECTRONICS

194 / 272 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

PSD module

UPSD33xx

194/272

Doc ID 9685 Rev 7

The AND-OR array is used to form product terms. These product terms are configured from

the logic definitions entered in PSDsoft Express. A PLD Input Bus consisting of 69 signals is

connected to both PLDs. Input signals are shown in Table 121 on page 194, both the true

and compliment versions of each of these signals are available at inputs to each PLD.

Note:

The 8032 data bus, D0 - D7, does not route directly to PLD inputs. Instead, the 8032 data

bus has indirect access to the GPLD (not the DPLD) when the 8032 reads and writes the

OMC and IMC registers within csiop address space.

27.4.25

Turbo Bit and PLDs

The PLDs can minimize power consumption by going to standby after ALL the PLD inputs

remain unchanged for an extended time (about 70ns). When the Turbo Bit is set to logic one

(Bit 3 of the csiop PMMR0 register), Turbo mode is turned off and then this automatic

standby mode is achieved. Turning off Turbo mode increases propagation delays while

reducing power consumption. The default state of the Turbo Bit is logic zero, meaning Turbo

mode is on. Additionally, four bits are available in the csiop PMMR0 and PMMR2 registers to

block the 8032 bus control signals (RD, WR, PSEN, ALE) from entering the PLDs. This

reduces power consumption and can be used only when these 8032 control signals are not

used in PLD logic equations. See Section 27.4.51: Power management on page 224.

Table 121.

DPLD and GPLD inputs

Input source

Input name

Number of

signals

8032 address bus

A0-A15

8032 bus control signals

PSEN, RD, WR, ALE

Reset from MCU module

RESET

Power-down from Auto-Power-down counter

PDN

PortA Input macrocells

(80-pin devices only)

PA0-PA7

PortB input macrocells

PB0-PB7

PortC input macrocells

PC2, PC3, PC4, PC7

Port D inputs

(52-pin devices have only PD1)

PD1, PD2

Page register

PGR0-PGR7

Macrocell OMC bank AB feedback

MCELLAB

FB0-7

Macrocell OMC bank BC feedback

MCELLBC

FB0-7

Flash Memory Status bit

Ready/Busy

UPSD3312D bảng dữ liệu(PDF) 194 Page - STMicroelectronics

UPSD3312D bảng dữ liệu(HTML) 194 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL