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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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UPSD3312D bảng dữ liệu(PDF) 174 Page - STMicroelectronics |
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UPSD3312D bảng dữ liệu(HTML) 174 Page - STMicroelectronics |
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174 / 272 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD module UPSD33xx 174/272 Doc ID 9685 Rev 7 27.2.5 Alternative mapping schemes Here are more possible memory maps for the UPSD3333. Note: Mapping examples would be slightly different for UPSD3312, UPSD3334, and UPSD3354 because of the different sizes of individual Flash memory sectors and SRAM as defined in Table 119 on page 193. ● Figure 54 on page 174 Place the larger main Flash memory into program space, but split the secondary Flash in half, placing two of it’s sectors into XDATA space and remaining two sectors into program space. This method allows the designer to put IAP code (or boot code) into two sectors of secondary Flash in program space, and use the other two secondary Flash sectors for data storage, such as EEPROM emulation in XDATA space. ● Figure 55 on page 175 Place both the Main and secondary Flash memories into program space for maximum code storage, with no Flash memory in XDATA space. Figure 54. Mapping: split second Flash in half 0000h 8000h 4000h 6000h FFFFh 8032 XDATA SPACE (RD and WR) 8032 PROGRAM SPACE (PSEN) csboot1, 8KB Common Memory to All Pages csboot0, 8KB Common Memory to All Pages csboot2 8KB csboot3 8KB Page X rs0, 8KB csiop, 256B fs7 16KB fs3 16KB fs1 16KB Page 0 Page 1 Page 2 Page 3 2000h 0000h 8000h FFFFh Nothing Mapped fs6 16KB fs5 16KB fs4 16KB fs2 16KB fs0 16KB System I/O System I/O C000h 2100h 4000h 2000h AI09174 |
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