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AR0134CSSC00SUEAH-GEVB bảng dữ liệu(PDF) 40 Page - ON Semiconductor

tên linh kiện AR0134CSSC00SUEAH-GEVB
Giải thích chi tiết về linh kiện  Inch 1.2 Mp CMOS Digital Image Sensor with Global Shutter
PDF  41 Pages
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nhà sản xuất  ONSEMI [ON Semiconductor]
Trang chủ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

AR0134CSSC00SUEAH-GEVB bảng dữ liệu(HTML) 40 Page - ON Semiconductor

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AR0134_DS Rev. G Pub. 6/15 EN
40
©Semiconductor Components Industries, LLC,2015.
AR0134: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Revision History
Revision History
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/9/15
• Updated “Ordering Information” on page 2
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/29/15
• Updated “Ordering Information” on page 2
• Removed Confidential marking
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/19/14
• Updated to ON Semiconductor template
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/13/14
• Updated Table 1, “Key Parameters,” on page 1
• Updated Figure 4: “Typical Configuration: Serial Four-Lane HiSPi Interface,” on
page 10
• Updated Figure 6: “9x9mm 63-Ball iBGA Package,” on page 12
• Updated Table 5, “Two-Wire Serial Bus Characteristics,” on page 22
• Updated Table 6, “I/O Timing Characteristics, Parallel Output (1.8V VDD_IO)1,” on
page 24
• Updated Table 7, “I/O Timing Characteristics, Parallel Output (2.8V VDD_IO)1,” on
page 25
• Updated “Two-Wire Serial Register Interface” on page 17
• Split Table 6 and updated values in Table 8, “I/O Rise Slew Rate (2.8V VDD_IO)1,” on
page 26 and Table 9, “I/O Fall Slew Rate (2.8V VDD_IO)1,” on page 26
• Updated “Power-Up Sequence” on page 32
• Updated Figure 19: “Power Up,” on page 32
• Updated Figure 25: “63-Ball iBGA Package Outline Drawing,” on page 38
• Updated Figure 26: “48-pin iLCC Package Drawing,” on page 39
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/13/13
• Updated to Production
• Applied updated Aptina template
• Updated “General Description” on page 1
• Updated Table 1, “Key Parameters,” on page 1
• Updated Table 3, “Available Part Numbers,” on page 3
• Updated “Features Overview” on page 7
• Added “Pixel Data Format” on page 8
• Updated Table 6, “I/O Timing Characteristics, Parallel Output (1.8V VDD_IO)1,” on
page 24
• Updated Table 7, “I/O Rise Slew Rate (2.8V Vdd_IO)1,” on page 23
• Updated Table 8, “I/O Fall Slew Rate (2.8V Vdd_IO)1,” on page 23
• Updated Table 9, “I/O Rise Slew Rate (1.8V Vdd_IO)1,” on page 23
• Added “Two-Wire Serial Register Interface” on page 17
• Added “Standby Sequence” on page 34
• Added Table 20, “Chief Ray Angle - 25deg Mono,” on page 37
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/23/13
• Updated to Preliminary
• Updated “Features” on page 1



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