AR0134CSSC00SUEAH-GEVB datasheet(13/41 Pages) ONSEMI

13 / 41 page

AR0134_DS Rev. G Pub. 6/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0134: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

Configuration and Pinout

Table 3:

Pin Descriptions - 63-Ball iBGA Package

Name

iBGA Pin

Type

Description

SLVS0_N

Output

HiSPi serial data, lane 0, differential N.

SLVS0_P

Output

HiSPi serial data, lane 0, differential P.

SLVS1_N

Output

HiSPi serial data, lane 1, differential N.

SLVS1_P

Output

HiSPi serial data, lane 1, differential P.

STANDBY

Input

Standby-mode enable pin (active HIGH).

VDD_PLL

Power

PLL power.

SLVSC_N

Output

HiSPi serial DDR clock differential N.

SLVSC_P

Output

HiSPi serial DDR clock differential P.

SLVS2_N

Output

HiSPi serial data, lane 2, differential N.

SLVS2_P

Output

HiSPi serial data, lane 2, differential P.

VAA

B7, B8

Power

Analog power.

EXTCLK

Input

External input clock.

VDD_SLVS

Power

HiSPi power. (May leave unconnected if parallel interface is used)

SLVS3_N

Output

(Unsupported) HiSPi serial data, lane 3, differential N.

SLVS3_P

Output

(Unsupported) HiSPi serial data, lane 3, differential P.

DGND

C5, D4, D5, E5, F5, G5, H5

Power

Digital GND.

VDD

A6, A7, B6, C6, D6

Power

Digital power.

AGND

C7, C8

Power

Analog GND.

SADDR

Input

Two-Wire Serial address select.

SCLK

Input

Two-Wire Serial clock input.

SDATA

I/O

Two-Wire Serial data I/O.

VAA_PIX

D7, D8

Power

Pixel power.

LINE_VALID

Output

Asserted when DOUT line data is valid.

FRAME_VALID

Output

Asserted when DOUT frame data is valid.

PIXCLK

Output

Pixel clock out. DOUT is valid on rising edge of this clock.

FLASH

Output

Control signal to drive external light sources.

VDD_IO

E6, F6, G6, H6, H7

Power

I/O supply power.

DOUT8

Output

Parallel pixel data output.

DOUT9

Output

Parallel pixel data output.

DOUT10

Output

Parallel pixel data output.

DOUT11

Output

Parallel pixel data output (MSB)

TEST

Input

Manufacturing test enable pin (connect to DGND).

DOUT4

Output

Parallel pixel data output.

DOUT5

Output

Parallel pixel data output.

DOUT6

Output

Parallel pixel data output.

DOUT7

Output

Parallel pixel data output.

TRIGGER

Input

Exposure synchronization input. (Connect to DGND if HiSPi interface is

used)

OE_BAR

Input

Output enable (active LOW).

DOUT0

Output

Parallel pixel data output (LSB)

DOUT1

Output

Parallel pixel data output.

DOUT2

Output

Parallel pixel data output.

DOUT3

Output

Parallel pixel data output.

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