AR0134CSSC00SUEAH-GEVB datasheet(24/41 Pages) ONSEMI

24 / 41 page

AR0134_DS Rev. G Pub. 6/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0134: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

Electrical Specifications

I/O Timing

By default, the AR0134 launches pixel data, FV and LV with the falling edge of PIXCLK.

The expectation is that the user captures DOUT[11:0], FV and LV using the rising edge of

PIXCLK. The launch edge of PIXCLK can be configured in register R0x3028. See Figure 15

and Table 6 for I/O timing (AC) characteristics.

Figure 15:

I/O Timing Diagram

Table 6:

I/O Timing Characteristics, Parallel Output (1.8V VDD_IO)1

Symbol

Definition

Condition

Min

Typ

Max

Unit

fEXTCLK

Input clock frequency

650

MHz

tEXTCLK

Input clock period

166

Input clock rise time

PLL enabled

3ns

Input clock fall time

PLL enabled

3ns

tjJITTER

Input clock jitter

600

tcp

EXTCLK to PIXCLK propagation

delay

Nominal voltages, PLL disabled,

PIXCLK slew rate = 4

5.7

14.3

tRP

PIXCLK rise time

PCLK slew rate = 6

1.3

4.0

tFP

PIXCLK fall time

PCLK slew rate = 6

1.3

3.9

PIXCLK duty cycle

fPIXCLK

PIXCLK frequency

PIXCLK slew rate = 6,

Data slew rate = 7

74.25

MHz

tPD

PIXCLK to data valid

PIXCLK slew rate = 6,

Data slew rate = 7

-2.5

tPFH

PIXCLK to FV HIGH

PIXCLK slew rate = 6,

Data slew rate = 7

-2.5

tPLH

PIXCLK to LV HIGH

PIXCLK slew rate = 6,

Data slew rate = 7

-3

1.5

tPFL

PIXCLK to FV LOW

PIXCLK slew rate = 6,

Data slew rate = 7

-2.5

tPLL

PIXCLK to LV LOW

PIXCLK slew rate = 6,

Data slew rate = 7

-3

1.5

CIN

Input pin capacitance

2.5

Data[11:0]

LINE_VALID/

PIXCLK

EXTCLK

tEXTCLK

FRAME_VALID leads LINE_VALID by 6 PIXCLKs.

FRAME_VALID trails

LINE_VALID by 6 PIXCLKs.

tPLH

tPFH

tPFL

tPLL

tPD

Pxl _0

Pxl _1

Pxl _2

Pxl _n

90%

10%

tRP

tFP

90%

10%

FRAME_VALID

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