AR0134CSSC00SUEAH-GEVB datasheet(30/41 Pages) ONSEMI

30 / 41 page

AR0134_DS Rev. G Pub. 6/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0134: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

Electrical Specifications

Figure 16:

Differential Output Voltage for Clock or Data Pairs

Notes:

1. One UI is defined as the normalized mean time between one edge and the following edge of the

clock.

2. Taken from 0V crossing point.

3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance

may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum

0.3UI.

4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any

edges.

5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY

between any edges.

6. Differential skew is defined as the skew between complementary outputs. It is measured as the

absolute time between the two complementary edges at mean VCM point.

Table 17:

Rise and Fall Times

Measurement Conditions: HiSPi Power Supply 0.4V, Max Freq 700 MHz

Parameter

Symbol

Min

Typ

Max

Unit

Data Rate

1/UI

280

–

700

Mb/s

Max setup time from transmitter

TxPRE

0.3

–

UI1

Max hold time from transmitter

TxPost

0.3

–

Rise time (20% - 80%)

RISE

–

0.25UI

–

Fall time (20% - 80%)

FALL

150ps

0.25 UI

–

Clock duty

PLL_DUTY

Bitrate Period

tpw

1.43

3.57

ns1

Eye Width

teye

0.3

UI1, 2

Data Total jitter (pk pk)@1e-9

ttotaljit

0.2

UI1, 2

Clock Period Jitter (RMS)

tckjit

ps2

Clock cycle to cycle jitter (RMS)

tcyjit

100

ps2

Clock to Data Skew

tchskew

-0.1

0.1

UI1, 2

PHY-to-PHY Skew

t|PHYskew|

2.1

UI1, 5

Mean differential skew

tDIFFSKEW

–100

100

ps6

0V Diff)

VDIFFmax

VDIFFmin

Output Signal is 'Cp - Cn' or 'Dp - Dn'

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