AR0134CSSC00SUEAH-GEVB datasheet(22/41 Pages) ONSEMI

22 / 41 page

AR0134_DS Rev. G Pub. 6/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0134: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

Electrical Specifications

Unless otherwise stated, the following specifications apply to the following conditions:

VDD = 1.8V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V ± 0.3V;

VDD_SLVS = 0.4V – 0.1/+0.2; TA = -30°C to +70°C; output load = 10pF;

PIXCLK frequency = 74.25 MHz; HiSPi off.

Two-Wire Serial Register Interface

The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are

shown in Figure 14 and Table 5.

Figure 14:

Two-Wire Serial Bus Timing Parameters

Note:

Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register

address are issued.

Table 5:

Two-Wire Serial Bus Characteristics

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C

Parameter

Symbol

Standard-Mode

Fast-Mode

Unit

Min

Max

Min

Max

SCLK Clock Frequency

fSCL

100

400

KHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

tHD;STA

4.0

0.6

S

LOW period of the SCLK clock

tLOW

4.7

1.3

S

HIGH period of the SCLK clock

tHIGH

4.0

0.6

S

Set-up time for a repeated START

condition

tSU;STA

4.7

0.6

S

Data hold time:

tHD;DAT

3.455

0.95

S

Data set-up time

tSU;DAT

250

1006

-nS

Rise time of both SDATA and SCLK signals

1000

20 + 0.1Cb7

300

Fall time of both SDATA and SCLK signals

300

20 + 0.1Cb7

300

tSU;STO

tSU;STA

tHD;STA

tHIGH

tLOW

tSU;DAT

tHD;DAT

SDATA

SCLK

tBUF

tHD;STA

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