UPD78323LP datasheet(32/86 Pages) NEC

tên linh kiện	UPD78323LP

Giải thích chi tiết về linh kiện	16/8-BIT SINGLE-CHIP MICROCONTROLLER

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nhà sản xuất	NEC [NEC]

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µPD78323, 78324

3.6

CLOCK GENERATOR

The clock generator generates and controls internal system clocks (CLK) supplied to the CPU. It is configured as shown

in Figure 3-1.

Figure 3-1. Block Diagram of Clock Generator

STOP Mode

fXX or fX

1/2

fCLK

Internal System

Clock (CLK)

Divider

System

Clock

Generator

Remarks

fXX : Crystal oscillator frequency

: External clock frequency

fCLK : Internal system clock frequency

The system clock oscillator oscillates by a crystal resonator connected to X1 and X2 pins. It stops oscillating when set

to the standby mode (STOP).

External clocks can be input to the system clock oscillator. In such cases, input a clock signal to the X1 pin and input

the reverse phase of the clock signal to the X2 pin. The X2 pin can also be left open.

Caution

When using external clocks, do not set the STBC STP bit.

The divider generates internal system clocks (fCLK) by dividing a system clock oscillator output (fxx for crystal oscillation

and fx for external clocks) into two parts.

UPD78323LP bảng dữ liệu(PDF) 32 Page - NEC