UM0851 datasheet(164/245 Pages) STMICROELECTRONICS

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Accelerator engine device drivers

UM0851

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Doc ID 16604 Rev 2

requests from two channels become active at the same time, the channel with the

highest priority is serviced first.

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Two AHB bus masters for transferring data. Use these interfaces to transfer data when

a DMA request goes active.

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Incrementing or non-incrementing addressing for source and destination.

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Programmable DMA burst size. You can program the DMA burst size to transfer data

more efficiently. The burst size is usually set to half the size of the FIFO in the

peripheral.

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Supports eight, 16, and 32-bit wide transactions.

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Big-endian and little-endian support. The DMAC defaults to little-endian mode on reset.

6.2.2

Software overview

The DMAC driver is the software between the Linux DMA Engine framework and the ARM

PL080 DMA controller. It configures the hardware with the help of instructions passed from

the DMA framework or user driver.

The overall DMA software system architecture is represented in the figure below.

Figure 43.

DMA software architecture

DMA framework in Linux

The DMA Framework present in Linux provides a simple interface to client drivers wishing to

use DMA. Clients just register themselves with the DMA framework, request DMA channels,

transfer data on allocated DMA channels and finally get unregistered from the DMA

framework (unregistering also frees allocated DMA channels). To increase the performance

of the DMA driver, consistency related issues are handled by client drivers. They can

synchronize data between cache and RAM if source or destination memory is cached. If

memories are un-cached there is no need for synchronization.

The following paragraphs describe the steps that client driver needs to perform when

transferring data using DMA.

Kernel space

Hardware

Linux drivers

DMA engine framework

DMAC driver

DMAC ARM PL080

Memories and peripherals

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