UM0851 datasheet(139/245 Pages) STMICROELECTRONICS

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UM0851

Non-volatile memory device drivers

Doc ID 16604 Rev 2

139/245

give access to the Ready/Busy pin, then the function must not be defined and the function

pointer "dev_ready"(in struct mtd_info) is set to NULL.

The SPEAr platform can use the device ready functionality by enabling the option,

CONFIG_FSMC_WAIT_DISABLE in compilation config. Obviously this needs hardware

connection (connection of NAND Flash R/B pin to GPIO pin) in the SPEAr board as well.

5.2

EMI interface driver

5.2.1

Hardware overview

The EMI controller provide a simple external memory interface for acessing external NOR

Flash memory or FPGA devices using only a few signals. This block is designed to perform

simple read-write operations and does not support burst-type operations (either on the AHB

or on the EMI interface).

EMI is a generic interface for general data exchange (for example with NOR Flash). The

data exchange flow of the attached device must be broken down into simple operations and

should be performed in accordance with the EMI cycles.

Main features:

●

AHB slave interface

●

Multiplexed address and data bus

●

EMI is always master on the EMI bus

●

Performs 32, 16, 8 bit transfers

●

Can access 6 different peripherals using CS#, one at a time

●

Supports single transfer with an ACK signal from the external peripheral, which is used

to terminate the transfer

●

Supports peripherals which use Byte Lane procedure

Prior to any read/write operation, the Timing and Control registers must be programmed.

The timing registers are used to time the EMI-interface signals with respect to the HCLK

cycles. There are various registers for extending the EMI interface signals to a specified

number of HCLK cycles. The Control register provides information about the peripheral

connected.

When a write operation to the peripheral is requested, then an AHB write operation is

initiated. Similarly, for a read operation an AHB read is done. The EMI supports 8-bit, 16-bit

and 32-bit peripherals. The following table lists the transactions supported by EMI.

Table 40.

Supported transactions

Peripheral connected

AHB access

Support

32 bit

Yes

32 bit

16 bit

Yes

32 bit

8 bit

Yes

16 bit

32 bit

No (AHB Error, Interrupt)

16 bit

Yes

16 bit

8 bit

Yes

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