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UM0097 bảng dữ liệu(PDF) 40 Page - STMicroelectronics |
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UM0097 bảng dữ liệu(HTML) 40 Page - STMicroelectronics |
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40 / 229 page ![]() Peripheral firmware overview UM0097 40/229 RCCU_PLL2Config Example: This example illustrates how to set the PLL2 multiplication factor to 28 and the divider factor to 7. { ... RCCU_PLL2Config (RCCU_PLL2_Mul_28, RCCU_Div_7,4000000); ... } RCCU_RCLKSourceConfig Function Name RCCU_PLL2Config Function Prototype void RCCU_PLL2Config (RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div, u32 HCLK_Clock); Behavior Description Configures the PLL2 division and multiplication factors. Input Parameter 1 New_Mul: the PLL2 clock multiplication factor. Refer to PLL2 multiplication factors on page 32 for more details on the allowed values of this parameter. Input Parameter 2 New_Div: the PLL2 clock division factor. Refer to PLL division factors on page 32 for more details on the allowed values of this parameter. Input Parameter 3 HCLK_Clock: the clock value present on HCLK pin (in Hz). Output Parameter None Return Value None Required preconditions None Called Functions None Function Name RCCU_RCLKSourceConfig Function Prototype void RCCU_RCLKSourceConfig(RCLK_Clocks New_Clock); Behavior Description This routine selects the clock source for the RCLK. Input Parameter New_Clock: the RCLK clock source. Refer to RCLK clock source on page 31 for more details on the allowed values of this parameter. Output Parameter None Return Value None Required preconditions None Called Functions None |
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