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STM32F2xxxx devices bootloader

AN2606

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DocID13801 Rev 21

STM32F2xxxx devices bootloader

Two bootloader versions are available on STM32F2xxxx devices:

•

V2.0 supporting USART1 and USART3

This version is embedded in STM32F2xxxx devices revision B.

•

V3.2 supporting USART1, USART3, CAN2 and DFU (USB FS Device)

This version is embedded in STM32F2xxxx devices revision X and Y.

10.1

Bootloader V2.x

10.1.1

Bootloader configuration

The STM32F2xxxx bootloader is activated by applying pattern1 (described in Table 2:

Bootloader activation patterns). The following table shows the hardware resources used by

this bootloader.

Table 18. STM32F2xxxx configuration in System memory boot mode

Bootloader

Feature/Peripheral

State

Comment

Common to all

bootloaders

RCC

HSI enabled

The system clock frequency is 24 MHz.

RAM

8 Kbytes starting from address 0x2000

0000.

System memory

30688 bytes starting from address 0x1FFF

0000 contain the bootloader firmware.

IWDG

The independent watchdog (IWDG)

prescaler is configured to its maximum

value and is periodically refreshed to

prevent watchdog reset (in case the

hardware IWDG option was previously

enabled by the user).

Power

Voltage range is set to [1.62 V, 2.1 V]. In

this range internal Flash write operations

are allowed only in byte format (Half-Word,

Word and Double-Word operations are not

allowed). The voltage range can be

configured in run time using bootloader

commands.

USART1

bootloader

USART1

Enabled

Once initialized, the USART1 configuration

is: 8 bits, even parity and 1 Stop bit.

USART1_RX pin

Input

PA10 pin: USART1 in reception mode

USART1_TX pin

Output

PA9 pin: USART1 in transmission mode

USART3

bootloader (on

PC10/PC11)

USART3

Enabled

Once initialized, the USART3 configuration

is: 8 bits, even parity and 1 Stop bit.

USART3_RX pin

Input

PC11 pin: USART3 in reception mode

USART3_TX pin

Output

PC10 pin: USART3 in transmission mode

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