AN3393 datasheet(25/103 Pages) STMICROELECTRONICS

25 / 103 page

DocID018750 Rev 4

25/103

AN3393

103

The vector filter is a 7th-order anti-symmetric FIR filter. The 8 taps have a 4x2 structure:

VFC_1, VFC_2, VFC_3, VFC_4 and -VFC_1, -VFC_2, -VFC_3, -VFC_4.

The vector filter can be enabled or disabled by the VFILT bit in the CTRL_REG3 register.

For more information about the vector filter refer to Section 5.3.3.

4.12

THRS3 (1Fh)

Common threshold for overrun detection. The value is always unsigned (ABS) regardless of

the ABS settings in the SETT1/SETT2 registers. So, the THRS3 value is symmetric to the

zero level.

When the acceleration of any axis exceeds the THRS3 limit, the state machines are reset

(PPx = RPx). The reset of the state machines is enabled through the THR3_xA bits in the

SETT1/SETT2 registers.

4.13

CTRL_REG4 (20h)

1Dh

VFC_3

Coefficient 3

00h

1Eh

VFC_4

Coefficient 4

00h

Table 19. VFC register description (continued)

Add

Mnemonic

Definition

Default

Table 20. THRS3 register description

Bit

Name

THRS3_7

THRS3_6

THRS3_5

THRS3_4

THRS3_3

THRS3_2

THRS3_1

THRS3_0

Default

00000000

Table 21. Control register 4 description

Bit

Name

ODR3

ODR2

ODR1

ODR0

BDU

ZEN

YEN

XEN

Default

00000111

Table 22. Description control register 4

ODR [3:0]

Data rate selection. Default value: 0h

(Other: refer to Table 23).

BDU

Block data update. Default value: 0

0: Continuous update

1: Output register not updated until MSB and LSB have been read.

For more information about BDU, refer to Section 2.1.3.

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