AN3393 datasheet(98/103 Pages) STMICROELECTRONICS

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First-in first-out (FIFO) buffer

AN3393

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to-Stream is in Stream mode and the interrupt condition disappears, the FIFO buffer returns

to Bypass mode because the INT_SM2 bit becomes zero.

It is recommended to latch the interrupt signal used as the stream trigger in order to avoid

losing interrupt events. If the selected interrupt is latched, it is needed to read the register

OUTS2 to clear the INT_SM2 bit; after reading, the INT_SM2 bit takes 2*ODR to go low.

In Stream mode the FIFO buffer continues filling. When the buffer is full, the OVRN bit is set

high and the next samples overwrite the oldest.

Figure 35. Bypass-to-Stream mode

Bypass-to-Stream can be used in order to start the acquisition when the configured interrupt

is generated.

10.3.6

Bypass-to-FIFO mode

This mode is a combination of the Bypass and FIFO modes previously described. In

Bypass-to-FIFO mode, the FIFO buffer starts operating in Bypass mode and switches to

FIFO mode when INT2 occurs.

Follow these steps for Bypass-to-FIFO mode configuration:

Configure State Machine 2 in order to generate interrupt on INT2.

Turn on FIFO by setting the FIFO_EN bit to “1” in control register 6 (25h). After this

operation the FIFO buffer is enabled but isn’t collecting data, output registers are

frozen to the last samples set loaded.

Activate Bypass-to-FIFO mode by setting the FMODE[2:0] field to “111” in the FIFO

control register (2Eh).

The interrupt trigger is related to the INT_SM2 bit in the STAT (18h) register and it is

generated even if the interrupt signal is not driven to an interrupt pad. Bypass-to-FIFO mode

is sensitive to the trigger level and not to the trigger edge, this means that if Bypass-to-FIFO

is in FIFO mode and the interrupt condition disappears, the FIFO buffer returns to Bypass

mode because the INT_SM2 bit becomes zero.

It is recommended to latch the interrupt signal used as the stream trigger in order to avoid

losing interrupt events. If INT2 is latched, it is necessary to read the register OUTS2 to clear

the INT_SM2 bit; after reading, the INT_SM2 bit takes 2*ODR to go low.

In FIFO mode the FIFO buffer collects data until it is full and then stops acquisition.

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