AN3393 datasheet(89/103 Pages) STMICROELECTRONICS

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AN3393

First-in first-out (FIFO) buffer

103

Table 95 represents the FIFO full status when 32 samples are stored in the buffer while

Table 96 represents the next step when the 33rd sample is inserted into FIFO and the 1st

sample is overwritten. The new oldest sample set is made available in the output registers.

When FIFO is enabled and the mode is different from Bypass, the output registers (28h to

2Dh) always contain the oldest FIFO sample set.

10.2

FIFO registers

The FIFO buffer is managed by three different accelerometer registers, two of these allow

FIFO behavior to be enabled and configured, the third provides information about the buffer

status.

10.2.1

Control register 6 (25h)

The FIFO_EN bit in CTRL_REG6 must be set to 1 in order to enable the internal first-in,

first-out buffer; while this bit is set, the LIS3DSH output registers (28h to 2Dh) do not contain

the current acceleration value but they always contain the oldest value stored in FIFO.

The WTM_EN bit can be used to limit the maximum FIFO buffer depth to WTMP[4:0] + 1.

The ADD_INC bit (default “1”) enables the address auto-increment during a serial interface

multiple byte access.

Table 96. FIFO overrun representation (33rd sample set stored and 1st sample

discarded)

Output

registers

28h

29h

2Ah

2Bh

2Ch

2Dh

Xl(1)

Xh(1)

Yl(1)

Yh(1)

Zl(1)

Zh(1)

FIFO index

Sample set

FIFO(0)

Xl(1)

Xh(1)

Yl(1)

Yh(1)

Zl(1)

Zh(1)

FIFO(1)

Xl(2)

Xh(2)

Yl(2)

Yh(2)

Zl(2)

Zh(2)

FIFO(2)

Xl(3)

Xh(3)

Yl(3)

Yh(3)

Zl(3)

Zh(3)

FIFO(3)

Xl(4)

Xh(4)

Yl(4)

Yh(4)

Zl(4)

Zh(4)

...

FIFO(30)

Xl(31)

Xh(31)

Yl(31)

Yh(31)

Zl(31)

Zh(31)

FIFO(31)

Xl(32)

Xh(32)

Yl(32)

Yh(32)

Zl(32)

Zh(32)

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