AN3393 datasheet(92/103 Pages) STMICROELECTRONICS

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First-in first-out (FIFO) buffer

AN3393

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The watermark flag, the FIFO overrun and FIFO empty event can be enabled to generate a

dedicated interrupt on the INT1 pin by configuring the CTRL_REG6 register.



P1_WTM bit drives the watermark flag (WTM) on the INT1 pin



P1_OVERRUN bit drives the overrun event (OVRN) on the INT1 pin



P1_EMPTY bit drives the empty event (EMPTY) on the INT1 pin.

If one or more bits is set to “1”, the INT1 pin status is the logical OR combination of the

selected signals.

10.3

FIFO modes

The LIS3DSH FIFO buffer can be configured to operate in six different modes selectable by

the FMODE[2:0] field in the FIFO_CTRL register. Available configurations ensure a high

level of flexibility and extend the number of functions usable in application development.

Bypass, FIFO, Stream, Stream-to-FIFO, Bypass-to-Stream and Bypass-to-FIFO modes are

described in the following paragraphs.

10.3.1

Bypass mode

When Bypass mode is enabled, FIFO is not operational: the buffer content is cleared, output

registers (28h to 2Dh) are frozen at the last value loaded, and the FIFO buffer remains

empty until another mode is selected.

Follow these steps for Bypass mode configuration:

Turn on FIFO by setting the FIFO_EN bit to “1” in control register 6 (25h). After this

operation the FIFO buffer is enabled but isn’t collecting data, output registers are

frozen to the last sample set loaded.

Activate Bypass mode by setting the FMODE[2:0] field to “000” in the FIFO control

20h.

Bypass mode must be used in order to stop and reset the FIFO buffer when a different

mode is operating. Note that placing the FIFO buffer into Bypass mode clears the whole

buffer content.

11111

t0 + 32/ODR

11111

t0 + 33/ODR

Table 101. FIFO_SRC_REG behavior assuming WTMP[4:0] = 15 (continued)

WTM

OVRN

Empty

FSS[4:0]

FIFO samples

Timing

Table 102. CTRL_REG6 (25h)

FIFO_EN

WTM_EN

ADD_INC

P1_

EMPTY

P1_WTM

P1_OVER

RUN

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