UM0434 datasheet(103/390 Pages) STMICROELECTRONICS

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UM0434

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Figure 6.

Parallel signature unit

The parallel signature unit consists of seven registers as described in this section. Access to

these registers is privileged. No user-mode access is allowed.

Note:

Proper access of the PSU registers requires an mfdcr that reads a PSU register to be

proceeded by either mbar or msync. To ensure that the effects of an mtdcr to one of the

PSU registers takes effect, the mtdcr is followed by a context synchronizing instruction (sc,

isync, rfi, rfci, rfdi).

4.19.1

Parallel signature control register (PSCR)

PSCR, shown in

Table 91, controls operation of the parallel signature unit.

PSCR field descriptions are shown in

Table 92.

d q

...

D31 (D63) D30 (D62)

D29 (D61) D28 (D60)

D1 (D33)

D0 (D32)

D21 (D53)

d q

D20 (D52)

d q

D22 (D54)

Data Bus (p_d_hrdata, p_d_hwdata)

PSHR, (PSLR)

Table 91.

Parallel signature control register (PSCR)

59 60

Field

—

CNTEN

—

RDEN

WREN

INIT

Reset

All zeros

R/W

DCR

DCR 272

Table 92.

PSCR field descriptions

Bits

Name

Description

32–57

—

Reserved, should be cleared.

CNTEN

Counter enable.

0 Counter is disabled.

1 Counter is enabled. Counter is incremented on every accumulated

transfer or on an mtdcr psulr,rS.

59–60

—

Reserved, should be cleared.

RDEN

Read enable.

0 Processor data read cycles are ignored.

1 Processor data reads cycles are accumulated. For inactive byte lanes,

zeros are used for the data values.

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