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376 EMBEDDED PROCESSOR

The AC specifications given in Table 64 consist of

output delays input setup requirements and input

hold requirements All AC specifications are rela-

tive to the CLK2 rising edge crossing the 20V level

AC specification measurement is defined by Figure

61 Inputs must be driven to the voltage levels indi-

cated by Figure 61 when AC specifications are

measured 80376 output delays are specified with

minimum and maximum limits measured as shown

The minimum 80376 delay times are hold times pro-

vided to external circuitry 80376 input setup and

hold times are specified as minimums defining the

smallest acceptable sampling window Within the

sampling window a synchronous input signal must

be stable for correct 80376 processor operation

Outputs NA WR DC MIO LOCK BHE BLE

A23–A1 and HLDA only change at the beginning of

phase one D15–D0 (write cycles) only change at the

beginning of phase two The READY HOLD BUSY

ERROR PEREQ and D15–D0 (read cycles) inputs

are sampled at the beginning of phase one The NA

INTR and NMI inputs are sampled at the beginning

of phase two

240182 – 35

LEGEND

AMaximum Output Delay Spec

BMinimum Output Delay Spec

CMinimum Input Setup Spec

DMinimum Input Hold Spec

Figure 61 Drive Levels and Measurement Points for AC Specifications

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