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376 bảng dữ liệu(PDF) 44 Page - Intel Corporation

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Giải thích chi tiết về linh kiện  376TM HIGH PERFORMANCE 32-BIT EMBEDDED PROCESSOR
PDF  95 Pages
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nhà sản xuất  INTEL [Intel Corporation]
Trang chủ  http://www.intel.com
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376 bảng dữ liệu(HTML) 44 Page - Intel Corporation

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376 EMBEDDED PROCESSOR
240182 – 22
Idle states are shown here for diagram variety only Write cycles are not always followed by an idle state An active bus
cycle can immediately follow the write cycle
Figure 47 Various Non-Pipelined Bus Cycles (Various Number of Wait States)
Figure 47 illustrates non-pipelined bus cycles with
one wait state added to Cycles 2 and 3 READY is
sampled inactive at the end of the first T2 in Cycles
2 and 3 Therefore Cycles 2 and 3 have T2 repeated
again At the end of the second T2 READY is sam-
pled active
When address pipelining is not used the address
and bus cycle definition remain valid during all wait
states When wait states are added and it is desir-
able to maintain non-pipelined timing it is necessary
to negate NA during each T2 state except the
last one as shown in Figure 47 Cycles 2 and 3 If
NA is sampled active during a T2 other than the last
one the next state would be T2I or T2P instead of
another T2
When address pipelining is not used the bus states
and transitions are completely illustrated by Figure
48
The bus transitions between four possible
states T1 T2 Ti and Th Bus cycles consist of T1
and T2 with T2 being repeated for wait states Oth-
erwise the bus may be idle Ti or in the hold ac-
knowledge state Th
44



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