376 datasheet(89/95 Pages) INTEL

89 / 95 page

376 EMBEDDED PROCESSOR

ENCODING OF THE SEGMENT

The sreg field in certain instructions is a 2-bit field

allowing one of the CS DS ES or SS segment regis-

ters to be specified The sreg field in other instruc-

tions is a 3-bit field allowing the FS and GS segment

registers to be specified also

2-Bit sreg2 Field

2-Bit

Segment

sreg2 Field

Selected

3-Bit sreg3 Field

3-Bit

Segment

sreg3 Field

Selected

000

001

010

011

100

101

110

do not use

111

do not use

ENCODING OF ADDRESS MODE

Except for special instructions such as PUSH or

POP where the addressing mode is pre-determined

the addressing mode for the current instruction is

specified by addressing bytes following the primary

opcode The primary addressing byte is the ‘‘mod

rm’’ byte and a second byte of addressing informa-

tion the ‘‘s-i-b’’ (scale-index-base) byte can be

specified

The s-i-b byte (scale-index-base byte) is specified

when using 32-bit addressing mode and the ‘‘mod

rm’’ byte has rm e 100 and mod e 00 01 or 10

When the sib byte is present the 32-bit addressing

mode is a function of the mod ss index and base

fields

The primary addressing byte the ‘‘mod rm’’ byte

also contains three bits (shown as TTT in Figure 81)

sometimes used as an extension of the primary op-

code The three bits however may also be used as

a register field (reg)

When calculating an effective address either 16-bit

addressing or 32-bit addressing is used 16-bit ad-

dressing uses 16-bit address components to calcu-

late the effective address while 32-bit addressing

uses 32-bit address components to calculate the ef-

fective address When 16-bit addressing is used the

‘‘mod rm’’ byte is interpreted as a 16-bit addressing

mode specifier When 32-bit addressing is used the

‘‘mod rm’’ byte is interpreted as a 32-bit addressing

mode specifier

Tables on the following three pages define all en-

codings of all 16-bit addressing modes and 32-bit

addressing modes

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