376 datasheet(46/95 Pages) INTEL

46 / 95 page

376 EMBEDDED PROCESSOR

240182 – 24

Following any idle bus state (Ti) bus cycles are non-pipelined Within non-pipelined bus cycles NA is only sampled

during wait states Therefore to begin pipelining during a group of non-pipelined bus cycles requires a non-pipelined

cycle with at least one wait state (Cylcle 2 above)

Figure 49 Transitioning to Pipelining during Burst of Bus Cycles

If NA is sampled active the 80376 is free to drive the

address and bus cycle definition of the next bus cy-

cle and assert ADS as soon as it has a bus request

internally pending It may drive the next address as

early as the next bus state whether the current bus

cycle is acknowledged at that time or not

Regarding the details of pipelining the 80376 has

the following characteristics

1 The next address and status may appear as early

as the bus state after NA was sampled active (see

Figures 49 or 410) In that case state T2P is

entered immediately However when there is not

an internal bus request already pending the next

address and status will not be available immedi-

ately after NA is asserted and T2I is entered in-

stead of T2P (see Figure 411 Cycle 3) Provided

the

current

bus

cycle

isn’t

yet

acknow-

ledged by READY asserted T2P will be entered

as soon as the 80376 does drive the next address

and status External hardware should therefore

observe the ADS output as confirmation the next

address and status are actually being driven on

the bus

2 Any address and status which are validated by a

pulse on the 80376 ADS output will remain stable

on the address pins for at least two processor

clock periods The 80376 cannot produce a new

address and status more frequently than every

two processor clock periods (see Figures 49

410 and 411)

3 Only the address and bus cycle definition of the

very next bus cycle is available The pipelining ca-

pability cannot look further than one bus cycle

ahead (see Figure 411 Cycle 1)

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