WM1811A datasheet(154/328 Pages) WOLFSON

154 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

154

WM1811A

Processor

WM1811A

or similar

CODEC

ADCDAT

LRCLK

DACDAT

BCLK

ADCDAT

LRCLK

DACDAT

BCLK

Figure 49 TDM with Processor as Master

Note: The WM1811A is a 24-bit device. If the user operates the WM1811A in 32-bit mode then the 8

LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore

recommended to add a pull-down resistor if necessary to the DACDAT line and the ADCDAT line in

TDM mode.

AUDIO DATA FORMATS (NORMAL MODE)

The audio data modes supported by the WM1811A are described below. Note that the polarity of the

BCLK and LRCLK signals can be inverted if required; the following descriptions all assume the

default, non-inverted polarity of these signals.

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency

and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 50 Right Justified Audio Interface (assuming n-bit word length)

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

WM1811A bảng dữ liệu(PDF) 154 Page - Wolfson Microelectronics plc