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WM1811A bảng dữ liệu(PDF) 35 Page - Wolfson Microelectronics plc

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WM1811A bảng dữ liệu(HTML) 35 Page - Wolfson Microelectronics plc

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Production Data
WM1811A
w
PD, November 2013, Rev 4.1
35
DIGITAL AUDIO INTERFACE - TDM MODE
When TDM operation is used on the ADCDATn pins, it is important that two devices do not attempt to
drive the ADCDATn pin simultaneously. To support this requirement, the ADCDATn pins can be
configured to be tri-stated when not outputting data.
The timing of the ADCDATn tri-stating at the start and end of the data transmission is described in
Figure 5 below.
BCLK
ADCDAT
ADCDAT set-up time
ADCDAT release time
ADCDAT undriven (tri-state)
ADCDAT valid (CODEC output)
ADCDAT valid
ADCDAT undriven (tri-state)
Figure 5 Audio Interface Timing- TDM Mode
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER
MIN
TYP
MAX
UNIT
TDM Timing - Master Mode
ADCDATsetup time from BCLKfalling edge
0
ns
ADCDATrelease time from BCLKfalling edge
15
ns
TDM Timing - Slave Mode
ADCDAT setup time from BCLK falling edge
5
ns
ADCDAT release time from BCLK falling edge
32
ns



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