WM1811A datasheet(60/328 Pages) WOLFSON

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WM1811A

Production Data

PD, November 2013, Rev 4.1

AUDIO INTERFACE 1 (AIF1) OUTPUT DIGITAL MIXING

There are two digital mixers associated with the AIF1 output channels. The inputs to each AIF1 mixer

comprise signals from the ADC / Digital Microphone inputs and from AIF2.

Note that the Left/Right channels of AIF1 can be inverted or interchanged if required; see “Digital

Audio Interface Control”.

The AIF1 Left output channel is derived from the ADCL / DMIC (Left) and AIF2 (Left) inputs.The ADCL

/ DMIC (Left) path is enabled by ADC1L_TO_AIF1ADC1L, whilst the AIF2 (Left) path is enabled by

AIF2DACL_TO_AIF1ADC1L.

The AIF1 Right output channel is derived from the ADCR / DMIC (Right) and AIF2 (Right) inputs. The

ADCR / DMIC (Right) path is enabled by ADC1R_TO_AIF1ADC1R, whilst the AIF2 (Right) path is

enabled by AIF2DACR_TO_AIF1ADC1R.

The AIF1 output mixer controls are defined in Table 16.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1542 (0606h)

AIF1 ADC1

Left Mixer

Routing

ADC1L_TO_AIF

1ADC1L

Enable ADCL / DMIC (Left) to AIF1

(Left) output

0 = Disabled

1 = Enabled

AIF2DACL_TO_

AIF1ADC1L

Enable AIF2 (Left) to AIF1 (Left)

output

0 = Disabled

1 = Enabled

R1543 (0607h)

AIF1 ADC1

Right Mixer

Routing

ADC1R_TO_AIF

1ADC1R

Enable ADCR / DMIC (Right) to

AIF1 (Right) output

0 = Disabled

1 = Enabled

AIF2DACR_TO_

AIF1ADC1R

Enable AIF2 (Right) to AIF1 (Right)

output

0 = Disabled

1 = Enabled

Table 16 AIF1 Output Mixing

DIGITAL SIDETONE VOLUME AND FILTER CONTROL

There are two digital sidetone signal paths, STL and STR.

The STL source is either ADCL or DMICDAT (Left). The Left ADC data will be selected if the

corresponding ADC is enabled (ie. if ADCL_ENA = 1). The Left digital microphone (DMIC) data will be

selected if the corresponding ADC is disabled (ie. if ADCL_ENA = 0).

The STR source is either ADCR or DMICDAT (Right). The Right ADC data will be selected if the

corresponding ADC is enabled (ie. if ADCR_ENA = 1). The Right digital microphone (DMIC) data will

be selected if the corresponding ADC is disabled (ie. if ADCR_ENA = 0).

See “Analogue to Digital Converter (ADC)” for details of the ADC control registers.

A digital volume control is provided for the digital sidetone paths. The associated register controls are

described in Table 17.

A digital high-pass filter can be enabled in the sidetone paths to remove DC offsets. This filter is

enabled using the ST_HPF register bit; the cut-off frequency is configured using ST_HPF_CUT. When

the filter is enabled, it is enabled in both digital sidetone paths.

Note that the sidetone filter cut-off frequency scales according to the sample rate of AIF1 or AIF2.

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the ST_HPF cut-off

frequency is scaled according to the AIF1_SR register. When AIF2CLK is selected as the SYSCLK

source (SYSCLK_SRC = 1), then the ST_HPF cut-off frequency is scaled according to the AIF2_SR

registers.

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