WM1811A datasheet(147/328 Pages) WOLFSON

tên linh kiện	WM1811A

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Production Data

WM1811A

PD, November 2013, Rev 4.1

147

OPCLK CLOCK OUTPUT

A clock output (OPCLK) derived from SYSCLK may be output on any GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”. This clock is enabled by register bit

OPCLK_ENA, and its frequency is controlled by OPCLK_DIV.

See “Clocking and Sample Rates” for more details of the System Clock (SYSCLK).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (0002h)

Power

Management

(2)

OPCLK_EN

GPIO Clock Output (OPCLK) Enable

0 = Disabled

1 = Enabled

R521 (0209h)

Clocking 1

2:0

OPCLK_DIV

000

GPIO Output Clock (OPCLK) Divider

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

Table 83 OPCLK Control

FLL CLOCK OUTPUT

The FLL Clock outputs may be outputdirectly on any GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

See “Clocking and Sample Rates” for more details of the WM1811A system clocking and for details of

how to enable and configure the Frequency Locked Loops.

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