WM1811A datasheet(146/328 Pages) WOLFSON

146 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

146

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1344

(0540h)

AIF2 DRC (1)

15:11

AIF2DRC_SIG_D

ET_RMS [4:0]

00000

AIF2 DRC Signal Detect RMS

Threshold.

This is the RMS signal level for signal

detect to be indicated when

AIF2DRC_SIG_DET_MODE=1.

00000 = -30dB

00001 = -31.5dB

…. (1.5dB steps)

11110 = -75dB

11111 = -76.5dB

10:9

AIF2DRC_SIG_D

ET_PK [1:0]

AIF2 DRC Signal Detect Peak

Threshold.

This is the Peak/RMS ratio, or Crest

Factor, level for signal detect to be

indicated when

AIF2DRC_SIG_DET_MODE=0.

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

AIF2DRC_SIG_D

ET_MODE

AIF2 DRC Signal Detect Mode

0 = Peakthreshold mode

1 = RMSthreshold mode

AIF2DRC_SIG_D

AIF2 DRC Signal Detect Enable

0 = Disabled

1 = Enabled

Table 82 DRC Signal Activity Detect GPIO/Interrupt Control

DIGITAL CORE FIFO ERROR STATUS DETECTION

The WM1811A monitors the Digital Core for error conditions which may occur if a clock rate mismatch

is detected. Under these conditions, the digital audio may become corrupted.

The most likely cause of a Digital Core FIFO Error condition is an incorrect system clocking

configuration. See “Clocking and Sample Rates” for the WM1811A system clocking requirements.

The Digital Core FIFO Error function is provided in order that the systemconfiguration can be verified

during product development.

The FIFO Error signal may be output directly on any GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

The FIFO Error signal is an input to the Interrupt control circuit. An interrupt event is triggered on the

rising edge of the FIFO Error signal. The associated interrupt bit is latched once set; it can be polled at

any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event

handling.

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