CY8C58LP datasheet(80/122 Pages) CYPRESS

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PSoC® 5LP: CY8C58LP Family

Datasheet

Document Number: 001-84932 Rev. **

Page 80 of 122

11.5.2 Delta-Sigma ADC

Unless otherwise specified, operating conditions are:

■ Operation in continuous sample mode

■ fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits

■ Reference = 1.024 V internal reference bypassed on P3.2 or P0.3

■ Unless otherwise specified, all charts and graphs show typical values

Notes

40. Based on device characterization (not production tested).

41. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional

to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.

Table 11-20. 20-bit Delta-sigma ADC DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Resolution

–

bits

Number of channels, single ended

–

No. of

GPIO

–

Number of channels, differential

Differential pair is formed using a

pair of GPIOs.

––

No. of

GPIO/2

–

Monotonic

Yes

–

Gain error

Buffered, buffer gain = 1, Range =

±1.024 V, 16-bit mode, 25 °C

––

±0.4

Gain drift

Buffered, buffer gain = 1, Range =

±1.024 V, 16-bit mode

––

ppm/°C

Vos

Input offset voltage

Buffered, 16-bit mode, full voltage

range, 25 °C

––

±0.2

Buffered, 16-bit mode, VDDA = 1.7 V,

25 °C

––

±0.1

TCVos

Temperature coefficient, input offset

voltage

Buffer gain = 1, 16-bit,

Range = ±1.024 V

–

0.55

µV/°C

Input voltage range, single ended[40]

VSSA

–VDDA

Input voltage range, differential unbuf-

fered[40]

VSSA

–VDDA

Input voltage range, differential,

buffered[40]

VSSA

–VDDA – 1

PSRRb

Power supply rejection ratio, buffered[40]

Buffer gain = 1, 16-bit,

Range = ±1.024 V

–

CMRRb

Common mode rejection ratio, buffered[40] Buffer gain = 1, 16 bit,

Range = ±1.024 V

–

INL20

Integral non linearity[40]

Range = ±1.024 V, unbuffered

–

±32

LSB

DNL20

Differential non linearity[40]

Range = ±1.024 V, unbuffered

–

±1

LSB

INL16

Integral non linearity[40]

Range = ±1.024 V, unbuffered

–

±2

LSB

DNL16

Differential non linearity[40]

Range = ±1.024 V, unbuffered

–

±1

LSB

INL12

Integral non linearity[40]

Range = ±1.024 V, unbuffered

–

±1

LSB

DNL12

Differential non linearity[40]

Range = ±1.024 V, unbuffered

–

±1

LSB

INL8

Integral non linearity[40]

Range = ±1.024 V, unbuffered

–

±1

LSB

DNL8

Differential non linearity[40]

Range = ±1.024 V, unbuffered

–

±1

LSB

Rin_Buff

ADC input resistance

Input buffer used

–

Rin_ADC16 ADC input resistance

Input buffer bypassed, 16-bit,

Range = ±1.024 V

–74[41]

–k

Rin_ADC12 ADC input resistance

Input buffer bypassed, 12 bit,

Range = ±1.024 V

–148[41]

–k

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