CY8C58LP datasheet(57/122 Pages) CYPRESS

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PSoC® 5LP: CY8C58LP Family

Datasheet

Document Number: 001-84932 Rev. **

Page 57 of 122

9. Programming, Debug Interfaces,

Resources

The Cortex-M3 has internal debugging components, tightly

integrated with the CPU, providing the following features:

■ JTAG or SWD access

■ Flash Patch and Breakpoint (FPB) block for implementing

breakpoints and code patches

■ Data Watchpoint and Trigger (DWT) block for implementing

watchpoints, trigger resources, and system profiling

■ Embedded Trace Macrocell (ETM) for instruction trace

■ Instrumentation Trace Macrocell (ITM) for support of printf-style

debugging

PSoC devices include extensive support for programming,

testing, debugging, and tracing both hardware and firmware.

Four interfaces are available: JTAG, SWD, SWV, and

TRACEPORT. JTAG and SWD support all programming and

debug features of the device. JTAG also supports standard JTAG

scan chains for board level test and chaining multiple JTAG

devices to a single JTAG connection. The SWV and

TRACEPORT provide trace output from the DWT, ETM, and

ITM. TRACEPORT is faster but uses more pins. SWV is slower

but uses only one pin.

For more information on PSoC 5 programming, refer to the

application note PSoC 5 Device Programming Specifications.

Cortex-M3 debug and trace functionality enables full device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator IDE software provides fully integrated

programming and debug support for PSoC devices. The low cost

MiniProg3 programmer and debugger is designed to provide full

programming and debug support of PSoC devices in conjunction

with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV

interfaces are fully compatible with industry standard third party

tools.

All Cortex-M3 debug and trace modules are disabled by default

and can only be enabled in firmware. If not enabled, the only way

to reenable them is to erase the entire device, clear flash

protection, and reprogram the device with new firmware that

enables them. Disabling debug and trace features, robust flash

protection, and hiding custom analog and digital functionality

inside the PSoC device provide a level of security not possible

with multichip application solutions. Additionally, all device

interfaces can be permanently disabled (Device Security) for

applications concerned about phishing attacks due to a

maliciously reprogrammed device. Permanently disabling

interfaces is not recommended in most applications because the

designer then cannot access the device later. Because all

programming, debug, and test interfaces are disabled when

Device Security is enabled, PSoCs with Device Security enabled

may not be returned for failure analysis.

9.1 JTAG Interface

The IEEE 1149.1 compliant JTAG interface exists on four or five

pins (the nTRST pin is optional). The JTAG clock frequency can

be up to 12 MHz, or 1/3 of the CPU clock frequency for 8 and

16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit

transfers, whichever is least. By default, the JTAG pins are

enabled on new devices but the JTAG interface can be disabled,

allowing these pins to be used as General Purpose I/O (GPIO)

instead. The JTAG interface is used for programming the flash

memory, debugging, I/O scan chains, and JTAG device chaining.

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