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SPEAR300 bảng dữ liệu(PDF) 46 Page - STMicroelectronics

tên linh kiện SPEAR300
Giải thích chi tiết về linh kiện  Embedded MPU with ARM926 core, flexible memory support, powerful connectivity features and human machine interface
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SPEAR300 bảng dữ liệu(HTML) 46 Page - STMicroelectronics

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PL_GPIO_8/C2
0
0
SD_WP
SD_WP
SD_WP
SD_WP
SD_WP
SD_WP
SD_WP
SD_WP
SD_WP
SD_WP
SD_WP
SSP_SCLK
PL_GPIO_7/D3
0
0
0
0
0
0
0
0
0
0000
SSP_SS
PL_GPIO_6/B1
0
0
SD_LED
SD_LED
SD_LED
SD_LED
SD_LED
SD_LED
SD_LED
SD_LED
SD_LED
SD_LED
SD_LED
SSP_MISO
PL_GPIO_5/D2
0
0
0
0
0
0
0
0
0
0000
I2C_SDA
PL_GPIO_4/C1
0
0
0
0
0
0
0
0
0
0000
I2C_SCL
PL_GPIO_3/D1
/E4
/E4
/E4
1
1
1
1
1
1
1111
UART_RX
PL_GPIO_2/E4
/E3
/E3
/E3
1
1
1
1
1
1
1111
UART_TX
PL_GPIO_1/E3
/E2
/E2
/E2
1
1
1
1
1
1
1111
IrDA_RX
PL_GPIO_0/F3
R/B
R/B
R/B
1
111
R/B
R/B
1111
IrDA_TX
PL_CK1/K17
TCLK*
TCLK*
CCLK/
TCLK*
TCLK*
CCLK/TC
LK*
TCLK*
CCLK/
TCLK*
TCLK*
TCLK*
TCLK*
CCLK/
TCLK*
TCLK*
CCLK/
TCLK*
PL_CLK1
Pl_CK2/J17
Reserved
Reserved
int_CLK
int_CLK
int_CLK
int_CLK
int_CLK
int_CLK
int_CLK
int_CLK
int_CLK
int_CLK
int_CLK
PL_CLK2
PL_CK3/J16
Reserved
Reserved
\int_CLK
\int_CLK
\int_CLK
\int_CLK
\int_CLK
\int_CLK
\int_CLK
CLK
CLK
CLK
CLK
PL_CLK3
PL_CK4/H17
Reserved
Reserved
2.048
MHz
2.048 MHz
2.048
MHz
2.048
MHz
2.048
MHz
2.048
MHz
2.048
MHz
PCLK
PCLK
PCLK
PCLK
PL_CLK4
Table 11.
PL_GPIO multiplexing scheme (continued)
PL_GPIO_# /
ball number
Configuration mode (enabled by RAS register 2)
Alternate
function
(enabled
by RAS
register 1)
1
2
3
4
5
6789
10
11
12
13



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