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SPEAR300 bảng dữ liệu(PDF) 76 Page - STMicroelectronics

tên linh kiện SPEAR300
Giải thích chi tiết về linh kiện  Embedded MPU with ARM926 core, flexible memory support, powerful connectivity features and human machine interface
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SPEAR300 bảng dữ liệu(HTML) 76 Page - STMicroelectronics

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Timing requirements
SPEAr300
76/83
Doc ID 16324 Rev 2
6.7.1
SPI master mode timings (clock phase = 0)
P = 1/SSP_CLK in nanoseconds (ns). For example, if the SSP_CLK frequency is 83 MHz,
use P = 12.048 ns
Table 45.
Timing requirements for SPI master mode (clock phase = 0)
No.
Parameters
Min
Max
Unit
13
tsu(DIV-CLKL)
Setup time, MISO (input)
valid before SSP_CLK
(output) rising edge
Clock
Polarity = 0
-0.411
-0.342
ns
14
tsu(DIV-CLKH)
Setup time, MISO (input)
valid before SSP_CLK
(output) falling edge
Clock
Polarity = 1
-0.411
-0.342
ns
15
th(CLKL-DIV)
Hold time, MISO
(input)valid after SSP_CLK
(output) rising edge
Clock
Polarity = 0
0.912
1.720
ns
16
th(CLKH-DIV)
Hold time, MISO (input)
valid after SSP_CLK
(output) falling edge
Clock
Polarity = 1
0.912
1.720
ns
Table 46.
Switching characteristics over recommended operating conditions for
SPI master mode (clock phase = 0)
No.
Parameters
Min
Max
Unit
17
td(CLKH-DOV)
Delay time, SSP_CLK
(output) falling edge to
MOSI (output) transition
Clock
Polarity = 0
-3.138
2.175
ns
18
td(CLKL-DOV)
Delay time, SSP_CLK
(output) rising edge to MOSI
(output) transition
Clock
Polarity = 1
-3.138
2.175
ns
19
td(ENL-CLKH/L)
Delay time, SSP_CSn (output) falling
edge to first SSP_CLK (output) rising or
falling edge
T/2
ns
20
td(CLKH/L-
ENH)
Delay time, SSP_CLK (output) rising or
falling edge to SSP_CSn (output) rising
edge
Tns



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