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44 / 83 page  PL_GPIO_51/D10 0 0 CLLP G10_6 CLLP G10_6 CLLP G10_6 G10_6 G10_6 CLLP G10_6 CLLP PL_GPIO_50/A12 0 0 CLLE G10_5 CLLE G10_5 CLLE G10_5 G10_5 G10_5 CLLE G10_5 CLLE TMR_CPTR4 PL_GPIO_49/C11 0 0 CLPP G10_4 CLPP G10_4 CLPP G10_4 G10_4 G10_4 CLPP G10_4 CLPP TMR_CPTR3 PL_GPIO_48/B11 B0 B0 CLD22 SPI_I2C0 SPI_I2C0 SPI_I2C0 SPI_I2C0 SPI_I2C0 SPI_I2C0 SPI_I2C0 DIO4_1 DIO4_1 SPI_I2C0 TMR_CPTR2 PL_GPIO_47/C10 B1 B1 CLD23 SPI_I2C1 SPI_I2C1 SPI_I2C1 SPI_I2C1 SPI_I2C1 SPI_I2C1 SPI_I2C1 DIO5_1 DIO5_1 SPI_I2C1 TMR_CPTR1 PL_GPIO_46/A11 B2 B2 GPIO7 SPI_I2C2 SPI_I2C2 SPI_I2C2 SPI_I2C2 SPI_I2C2 SPI_I2C2 SPI_I2C2 DIO6_1 DIO6_1 SPI_I2C2 TMR_CLK4 PL_GPIO_45/B10 B3 B3 GPIO6 SPI_I2C3 SPI_I2C3 SPI_I2C3 SPI_I2C3 SPI_I2C3 SPI_I2C3 SPI_I2C3 DIO7_1 DIO7_1 SPI_I2C3 TMR_CLK3 PL_GPIO_44/A10 H0 H0 GPIO5 G10_3/ DAC_O0 G10_3/ DAC_O0 G10_3/ DAC_O0 G10_3/ DAC_O0 G10_3 DAC_O0 DAC_O0 DAC_O0 DAC_O0 DAC_O0 TMR_CLK2 PL_GPIO_43/E9 H1 H1 GPIO4 G10_2/ DAC_O1 G10_2/ DAC_O1 G10_2/ DAC_O1 G10_2/ DAC_O1 G10_2 DAC_O1 DAC_O1 DAC_O1 DAC_O1 DAC_O1 TMR_CLK1 PL_GPIO_42/D9 H2 H2 GPIO3 I2S_DIN I2S_DIN I2S_DIN I2S_DIN G10_1 I2S_DIN I2S_DIN I2S_DIN I2S_DIN I2S_DIN UART_DTR PL_GPIO_41/C9 H3 H3 GPIO2 I2S_ LRCK I2S_ LRCK I2S_ LRCK I2S_ LRCK G10_0 I2S_LRC K I2S_LRCK I2S_LRCK I2S_LRCK I2S_LRCK UART_RI PL_GPIO_40/B9 H4 H4 GPIO1 I2S_CLK I2S_CLK I2S_CLK I2S_CLK TDM_SY NC3 I2S_CLK I2S_CLK I2S_CLK I2S_CLK I2S_CLK UART_DSR PL_GPIO_39/A9 H5 H5 GPIO0 I2S_ DOUT I2S_ DOUT I2S_ DOUT I2S_ DOUT TDM_SY NC2 DOUT I2S_DOUT I2S_DOUT I2S_DOUT I2S_DOUT UART_DCD PL_GPIO_38/A8 H6 H6 TDM_ SYNC1 TDM_ SYNC1 TDM_ SYNC1 TDM_ SYNC1 TDM_ SYNC1 TDM_ SYNC1 TDM_ SYNC1 TDM_ SYNC1 TDM_ SYNC1 TDM_ SYNC1 TDM_ SYNC1 UART_CTS PL_GPIO_37/B8 H7 H7 TDM_ DOUT TDM_ DOUT TDM_ DOUT TDM_ DOUT TDM_ DOUT TDM_ DOUT TDM_ DOUT TDM_ DOUT TDM_ DOUT TDM_ DOUT TDM_ DOUT UART_RTS PL_GPIO_36/C8 0 0 TDM_ SYNC0 TDM_ SYNC0 TDM_ SYNC0 TDM_ SYNC0 TDM_ SYNC0 TDM_ SYNC0 TDM_ SYNC0 TDM_ SYNC0 TDM_ SYNC0 TDM_ SYNC0 TDM_ SYNC0 SSP_CS4 PL_GPIO_35/D8 Reserved Reserved TDM_CLK TDM_CLK TDM_CLK TDM_CLK TDM_CLK TDM_CLK TDM_CLK TDM_CLK TDM_CLK TDM_CLK TDM_CLK SSP_CS3 PL_GPIO_34/E8 0 0 TDM_DIN TDM_DIN TDM_DIN TDM_DIN TDM_DIN TDM_DIN TDM_DIN TDM_DIN TDM_DIN TDM_DIN TDM_DIN SSP_CS2 PL_GPIO_33/E7 0 0 SD_CMD SD_CMD SD_CMD SD_CMD SD_CMD SD_CMD SD_CMD SD_CMD SD_CMD SD_CMD SD_CMD BasGPIO5 PL_GPIO_32/D7 0 0 SD_CLK SD_CLK SD_CLK SD_CLK SD_CLK SD_CLK SD_CLK SD_CLK SD_CLK SD_CLK SD_CLK BasGPIO4 PL_GPIO_31/C7 0 0 SD_DAT0 SD_DAT0 SD_DAT0 SD_DAT0 SD_DAT0 SD_DAT0 SD_DAT0 SD_DAT0 SD_DAT0 SD_DAT0 SD_DAT0 BasGPIO3 Table 11. PL_GPIO multiplexing scheme (continued) PL_GPIO_# / ball number Configuration mode (enabled by RAS register 2) Alternate function (enabled by RAS register 1) 1 2 3 4 5 6789 10 11 12 13 |
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