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SPEAR300 bảng dữ liệu(PDF) 45 Page - STMicroelectronics

tên linh kiện SPEAR300
Giải thích chi tiết về linh kiện  Embedded MPU with ARM926 core, flexible memory support, powerful connectivity features and human machine interface
PDF  83 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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SPEAR300 bảng dữ liệu(HTML) 45 Page - STMicroelectronics

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PL_GPIO_30/B7
0
0
SD_DAT1
SD_DAT1
SD_DAT1
SD_DAT1
SD_DAT1
SD_DAT1
SD_DAT1
SD_DAT1
SD_DAT1
SD_DAT1
SD_DAT1
BasGPIO2
PL_GPIO_29/A7
0
0
SD_DAT2
SD_DAT2
SD_DAT2
SD_DAT2
SD_DAT2
SD_DAT2
SD_DAT2
SD_DAT2
SD_DAT2
SD_DAT2
SD_DAT2
BasGPIO1
PL_GPIO_28/A6
0
0
SD_SDAT
3
SD_SDAT3
SD_SDAT
3
SD_SDAT
3
SD_SDAT
3
SD_SDAT
3
SD_SDAT
3
SD_SDAT
3
SD_SDAT
3
SD_SDAT
3
SD_SDAT
3
BasGPIO0
PL_GPIO_27/B6
0
0
SD_SDAT
4
SD_SDAT4
SD_SDAT
4
SD_SDAT
4
SD_SDAT
4
G8_0
G8_0
SD_SDAT
4
SD_SDAT
4
SD_SDAT
4
SD_SDAT
4
MII_TX_CLK
PL_GPIO_26/A5
0
0
SD_SDAT
5
SD_SDAT5
SD_SDAT
5
SD_SDAT
5
SD_SDAT
5
G8_1
G8_1
SD_SDAT
5
SD_SDAT
5
SD_SDAT
5
SD_SDAT
5
MII_TXD0
PL_GPIO_25/C6
0
0
SD_SDAT
6
SD_SDAT6
SD_SDAT
6
SD_SDAT
6
SD_SDAT
6
G8_2
G8_2
SD_SDAT
6
SD_SDAT
6
SD_SDAT
6
SD_SDAT
6
MII_TXD1
PL_GPIO_24/B5
0
0
SD_SDAT
7
SD_SDAT7
SD_SDAT
7
SD_SDAT
7
SD_SDAT
7
G8_3
G8_3
SD_SDAT
7
SD_SDAT
7
SD_SDAT
7
SD_SDAT
7
MII_TXD2
PL_GPIO_23/A4
0
0
G8_4
G8_4
G8_4
G8_4
G8_4
G8_4
G8_4
G8_4
G8_4
G8_4
G8_4
MII_TXD3
PL_GPIO_22/D6
0
0
G8_5
G8_5
G8_5
G8_5
G8_5
G8_5
G8_5
G8_5
G8_5
G8_5
G8_5
MII_TX_EN
PL_GPIO_21/C5
0
0
G8_6
G8_6
G8_6
G8_6
G8_6
G8_6
G8_6
DIO7
DIO8_1
DIO8_1
DIO7
MII_TX_ER
PL_GPIO_20/B4
0
0
G8_7
G8_7
G8_7
G8_7
G8_7
G8_7
G8_7
DIO6
DIO9_1
DIO9_1
DIO6
MII_RX_CLK
PL_GPIO_19/A3
0
0
G10_0
G10_0
G10_0
G10_0
G10_0
G10_0
G10_0
DIO5
DIO10_1
DIO10_1
DIO5
MII_RX_DV
PL_GPIO_18/D5
0
0
G10_1
G10_1
G10_1
G10_1
G10_1
G10_1
G10_1
DIO4
DIO11_1
DIO11_1
DIO4
MII_RX_ERR
PL_GPIO_17/C4
0
0
G10_2
G10_2
G10_2
G10_2
G10_2
G10_2
G10_2
DIO3
DIO12_1
DIO12_1
DIO3
MII_RXD0
PL_GPIO_16/E6
0
0
G10_3
G10_3
G10_3
G10_3
G10_3
G10_3
G10_3
DIO2
DIO13_1
DIO13_1
DIO2
MII_RXD1
PL_GPIO_15/B3
0
0
G10_4
G10_4
G10_4
G10_4
G10_4
G10_4
G10_4
DIO1
G10_4
G10_4
DIO1
MII_RXD2
PL_GPIO_14/A2
0
0
G10_5
G10_5
G10_5
G10_5
G10_5
G10_5
G10_5
DIO0
G10_5
G10_5
DIO0
MII_RXD3
PL_GPIO_13/A1
0
0
G10_6
G10_6
G10_6
G10_6
G10_6
G10_6
G10_6
VSYNC
G10_6
G10_6
VSYNC
MII_COL
PL_GPIO_12/D4
0
0
G10_7
G10_7
G10_7
G10_7
G10_7
G10_7
G10_7
HSYNC
G10_7
G10_7
HSYNC
MII_CRS
PL_GPIO_11/E5
0
0
G10_8
G10_8
G10_8
G10_8
G10_8
G10_8
G10_8
G10_8
G10_8
G10_8
G10_8
MII_MDC
PL_GPIO_10/C3
0
0
G10_9
G10_9
G10_9
G10_9
G10_9
G10_9
G10_9
G10_9
G10_9
G10_9
G10_9
MII_MDIO
PL_GPIO_9/B2
0
0
SD_CD
SD_CD
SD_CD
SD_CD
SD_CD
SD_CD
SD_CD
SD_CD
SD_CD
SD_CD
SD_CD
SSP_MOSI
Table 11.
PL_GPIO multiplexing scheme (continued)
PL_GPIO_# /
ball number
Configuration mode (enabled by RAS register 2)
Alternate
function
(enabled
by RAS
register 1)
1
2
3
4
5
6789
10
11
12
13



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