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SPEAR300 bảng dữ liệu(PDF) 61 Page - STMicroelectronics

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SPEAR300 bảng dữ liệu(HTML) 61 Page - STMicroelectronics

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SPEAr300
Timing requirements
Doc ID 16324 Rev 2
61/83
6.2.2
CLCD timing characteristics divided clock
Figure 15.
CLCD waveform with CLCP divided
Figure 16.
CLCD block diagram with CLCP divided
Table 105.
Note:
1
tSTABLE = tCLOCK direct max - (tmax + tmin)
2For tmax the maximum value is taken from the worst case and for tmin the minimum value is
taken from the best case.
3
CLCP should be delayed by {tmax + [tCLOCK direct max - (tmax + tmin)]/2} = 6.945 ns
Table 30.
CLCD timings with CLCP divided
Parameter
Value
Frequency
tCLOCK divided max
12 ns
83.3 MHz
tCLOCK divided max rise (tr)
0.81 ns
tCLOCK divided max (tf)
0.87 ns
tmin
-0.49 ns
tmax
2.38 ns
tSTABLE
9.13 ns
Tmin
Tmax
CLCP
CLD[23:0],CLAC,CLLE,CLLP,
CLFP,CLPOWER
Tclock
Tr
Tf
Tstable
Q
Q
SET
CLR
D
t2
CLCP
CLD[23:0],CLAC,CLLE,
CLLP,CLFP,CLPOWER
CLCDCLK
t1
Q
Q
SET
CLR
D
t3



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