C6416 datasheet(83/134 Pages) TI1

83 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

INPUT AND OUTPUT CLOCKS (CONTINUED)

Ideal Clock Period

ECLKIN

ECLKOUT1

Figure 20. ECLKOUT1 Timing for EMIFA and EMIFB Modules

switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA

and EMIFB modules†‡§ (see Figure 21)

NO.

PARAMETER

MIN

MAX

UNIT

tJ(EKO2)

Period jitter, ECLKOUT2

±175¶*

tw(EKO2H)

Pulse duration, ECLKOUT2 high

0.5NE − 0.7*

0.5NE + 0.7*

tw(EKO2L)

Pulse duration, ECLKOUT2 low

0.5NE − 0.7*

0.5NE + 0.7*

tt(EKO2)

Transition time, ECLKOUT2

td(EKIH-EKO2H) Delay time, ECLKIN high to ECLKOUT2 high

td(EKIH-EKO2L) Delay time, ECLKIN high to ECLKOUT2 low

*This parameter is not production tested.

† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

‡ These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are

prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.

§ E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.

N = the EMIF input clock divider; N = 1, 2, or 4.

¶ This period jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.

Ideal Clock Period

ECLKIN

ECLKOUT2

Figure 21. ECLKOUT2 Timing for the EMIFA and EMIFB Modules

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