C6416 datasheet(34/134 Pages) TI1

34 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

signal groups description (continued)

CLKR1/URADDR2†

Control/Status

CLKX1/URADDR4†

URDATA0

URDATA1

CLKS1/URADDR3†

URADDR1

URADDR0

Receive

URDATA7

URDATA4

URDATA3

URDATA2

URCLAV

URENB

URDATA5

URDATA6

URSOC

URCLK

Clock

Control/Status

Transmit

Clock

FSR1/UXADDR2†

DX1/UXADDR4†

UXDATA0

UXDATA1

FSX1/UXADDR3†

DR1/UXADDR1†

UXADDR0

UXDATA7

UXDATA4

UXDATA3

UXDATA2

UXCLAV

UXENB

UXDATA5

UXDATA6

UXSOC

UXCLK

UTOPIA (SLAVE) [C6415 and C6416 Only]

† For the C6415 and C6416 devices, these UTOPIA pins are MUXed with the McBSP1 peripheral. By default, these signals function as

McBSP1. For more details on these MUXed pins, see the Device Configurations section of this data sheet.

For the C6414 device, these McBSP1 peripheral pins are not MUXed; the C6414 does not support the UTOPIA peripheral.

TOUT0

Timers

TINP0

TOUT1

Timer 1

TINP1

TOUT2

Timer 2

TINP2

Timer 0

Figure 3. Peripheral Signals (Continued)

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