STM32F407IE datasheet(100/154 Pages) STMICROELECTRONICS

100 / 154 page

Electrical characteristics

STM32F405xx, STM32F407xx

100/154

Doc ID 022152 Rev 1

Table 52.

I2S characteristics(1)

TBD stands for “to be defined”.

Symbol

Parameter

Conditions

Min

Max

Unit

fCK

1/tc(CK)

I2S clock frequency

Master

TBD

37.5

MHz

Slave

37.5

tr(CK)

tf(CK)

I2S clock rise and fall time

capacitive load

CL = 50 pF

TBD

tv(WS)

(2)

Based on design simulation and/or characterization results, not tested in production.

WS valid time

Master

TBD

th(WS)

(2)

WS hold time

Master

TBD

tsu(WS)

(2)

WS setup time

Slave

TBD

th(WS)

(2)

WS hold time

Slave

TBD

tw(CKH)

(2)

tw(CKL)

(2)

CK high and low time

Master fPCLK= TBD,

presc = TBD

TBD

tsu(SD_MR)

(2)

tsu(SD_SR)

(2)

Data input setup time

Master receiver

Slave receiver

TBD

th(SD_MR)

(2)(3)

th(SD_SR)

(2)(3)

Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.

Data input hold time

Master receiver

Slave receiver

TBD

th(SD_MR)

(2)

th(SD_SR)

(2)

Data input hold time

Master fPCLK = TBD

Slave fPCLK = TBD

TBD

tv(SD_ST)

(2)(3)

Data output valid time

Slave transmitter

(after enable edge)

TBD

fPCLK = TBD

TBD

th(SD_ST)

(2)

Data output hold time

Slave transmitter

(after enable edge)

TBD

tv(SD_MT)

(2)(3)

Data output valid time

Master transmitter

(after enable edge)

TBD

fPCLK = TBD

TBD

th(SD_MT)

(2)

Data output hold time

Master transmitter

(after enable edge)

TBD

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