STM32F407IE datasheet(94/154 Pages) STMICROELECTRONICS

94 / 154 page

Electrical characteristics

STM32F405xx, STM32F407xx

94/154

Doc ID 022152 Rev 1

5.3.19

Communications interfaces

2C interface characteristics

Unless otherwise specified, the parameters given in Table 49 are derived from tests

performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage

conditions summarized in Table 10.

The STM32F405xx and STM32F407xx I

2C interface meets the requirements of the

standard I

2C communication protocol with the following restrictions: the I/O pins SDA and

SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and VDD is disabled, but is still present.

The I

2C characteristics are described in Table 49. Refer also to Section 5.3.16: I/O port

characteristics for more details on the input/output alternate function characteristics (SDA

and SCL).

Table 48.

Characteristics of TIMx connected to the APB2 domain(1)

TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.

Symbol

Parameter

Conditions

Min

Max

Unit

tres(TIM)

Timer resolution time

AHB/APB2

prescaler distinct

from 1, fTIMxCLK =

168 MHz

tTIMxCLK

5.95

AHB/APB2

prescaler = 1,

fTIMxCLK = 84 MHz

tTIMxCLK

11.9

fEXT

Timer external clock

frequency on CH1 to CH4

fTIMxCLK = 168 MHz

APB2 = 84 MHz

fTIMxCLK/2

MHz

084

MHz

ResTIM

Timer resolution

bit

tCOUNTER

16-bit counter clock

period when internal clock

is selected

65536

tTIMxCLK

0.00595

TBD

µs

tMAX_COUNT Maximum possible count

65536 × 65536

tTIMxCLK

TBD(2)

TBD stands for “to be defined”.

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