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STM32F407IE bảng dữ liệu(PDF) 80 Page - STMicroelectronics

tên linh kiện STM32F407IE
Giải thích chi tiết về linh kiện  USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32F407IE bảng dữ liệu(HTML) 80 Page - STMicroelectronics

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Electrical characteristics
STM32F405xx, STM32F407xx
80/154
Doc ID 022152 Rev 1
Jitter(5)
Master I2S clock jitter
Cycle to cycle at
12,343 MHz on
48KHz period,
N=432, P=4, R=5
RMS
-
90
-
peak
to
peak
-
±280
-
ps
Average frequency of
12,343 MHz
N=432, P=4, R=5
on 256 samples
TBD
-
TBD
ps
WS I2S clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-
400
-
ps
IDD(PLLI2S)
(6)
PLLI2S power consumption on
VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
IDDA(PLLI2S)
(6)
PLLI2S power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1.
TBD stands for “to be defined”.
2.
Take care of using the appropriate division factor M to have the specified PLL input clock values.
3.
Guaranteed by design, not tested in production.
4.
Maximum input PLL frequency is recommended for applications sensitive of long term jitter.
5.
Value given with main PLL running.
6.
Based on characterization, not tested in production.
Table 32.
PLLI2S (audio PLL) characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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