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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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IMX53CEC bảng dữ liệu(PDF) 165 Page - Freescale Semiconductor, Inc |
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IMX53CEC bảng dữ liệu(HTML) 165 Page - Freescale Semiconductor, Inc |
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165 / 204 page  Package Information and Contact Assignments i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 165 LVDS1_TX3_ N AA12 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[23] Input Floating LVDS1_TX3_P Y12 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[22] Input Floating NANDF_ALE Y11 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[8] Input 100 K Ω PU NANDF_CLE AA10 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[7] Input 100 K Ω PU NANDF_CS0 W12 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[11] Input 100 K Ω PU NANDF_CS1 V13 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[14] Input 100 K Ω PU NANDF_CS2 V14 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[15] Input 100 K Ω PU NANDF_CS3 W13 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[16] Input 100 K Ω PU NANDF_RB0 U11 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[10] Input 100 K Ω PU NANDF_RE_B AC8 NVCC_EIM_MAIN UHVIO ALT1 GPIO-6 gpio6_GPIO[13] Input 100 K Ω PU NANDF_WE_ B AB8 NVCC_EIM_MAIN UHVIO ALT1 GPIO-6 gpio6_GPIO[12] Input 100 K Ω PU NANDF_WP_ B AC9 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[9] Input 100 K Ω PU PATA_BUFFE R_EN K4 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[1] Input 100 K Ω PU PATA_CS_0 L5 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[9] Input 100 K Ω PU PATA_CS_1 L2 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[10] Input 100 K Ω PU PATA_DA_0 K6 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[6] Input 100 K Ω PU PATA_DA_1 L3 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[7] Input 100 K Ω PU PATA_DA_2 L4 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[8] Input 100 K Ω PU PATA_DATA0 L1 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[0] Input 100 K Ω PU PATA_DATA1 M1 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[1] Input 100 K Ω PU PATA_DATA10 N4 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[10] Input 100 K Ω PU PATA_DATA11 M6 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[11] Input 100 K Ω PU PATA_DATA12 N5 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[12] Input 100 K Ω PU PATA_DATA13 N6 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[13] Input 100 K Ω PU PATA_DATA14 P6 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[14] Input 100 K Ω PU PATA_DATA15 P5 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[15] Input 100 K Ω PU Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Contact Name Package Contact Assign ment Power Rail I/O Buffer Type Out of Reset Condition1 Alt. Mode Block I/O Direction Config./ Value |
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