IMX53CEC datasheet(46/204 Pages) FREESCALE

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i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Electrical Characteristics

4.6

System Modules Timing

This section contains the timing and electrical parameters for the modules in the i.MX53xD processor.

4.6.1

Reset Timings Parameters

Figure 8 shows the reset timing and Table 31 lists the timing parameters.

Figure 8. Reset Timing Diagram

4.6.2

WDOG Reset Timing Parameters

Figure 9 shows the WDOG reset timing and Table 32 lists the timing parameters.

Figure 9. WATCHDOG_RST Timing Diagram

NOTE

CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs.

4.6.3

Clock Amplifier Parameters (CKIH1, CKIH2)

The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave

or sinusoidal frequency source. No external series capacitors are required.

Table 31. Reset Timing Parameters

Parameter

Min

Max

Unit

CC1

Duration of RESET_IN to be qualified as valid (input slope = 5 ns)

—

Table 32. WATCHDOG_RST Timing Parameters

Parameter

Min

Max

Unit

CC5

Duration of WATCHDOG_RESET Assertion

—

TCKIL

RESET_IN

CC1

(Input)

WATCHDOG_RST

CC5

(Input)

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