IMX53CEC datasheet(68/204 Pages) FREESCALE

68 / 204 page

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Electrical Characteristics

Figure 31. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle

4.7

External Peripheral Interfaces Parameters

The following subsections provide information on external peripheral interfaces.

4.7.1

AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI

electrical specifications found within this document.

4.7.2

CSPI and ECSPI Timing Parameters

This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have

separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI

modules and the respective routing of these signals is shown in Table 45.

Table 44. DDR SDRAM Read Cycle 1

1 To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle

of DQ window.

Parameter

Symbol

SDCLK = 400 MHz

Unit

Min

Max

DDR26

Minimum required DQ valid window width

except from LPDDR2

—0.6

—

DDR26(LP

DDR2)

Minimum required DQ valid window width

for LPDDR2

—0.425

—

DDR27

DQS to DQ valid data

—

0.275

0.475

SDCLK

SDCLK_B

DQS (input)

DQ (input)

DATA

DDR26

DDR27

IMX53CEC bảng dữ liệu(PDF) 68 Page - Freescale Semiconductor, Inc

IMX53CEC bảng dữ liệu(HTML) 68 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL