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IMX53CEC bảng dữ liệu(PDF) 71 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  Applications Processors for Consumer Products
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IMX53CEC bảng dữ liệu(HTML) 71 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX53xD Applications Processors for Consumer Products, Rev. 2
Freescale Semiconductor
71
4.7.2.4
ECSPI Slave Mode Timing
Figure 33 depicts the timing of ECSPI in slave mode. Table 48 lists the ECSPI slave mode timing
characteristics.
4.7.3
Enhanced Serial Audio Interface (ESAI) Timing Parameters
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 49 shows the interface timing values. The number field in the table refers to timing signals
found in Figure 34 and Figure 35.
CS9
MISO Hold Time
tHmiso
0—
ns
CS10
RDY to SSx Time2
tSDRY
5—
ns
1 See specific I/O AC parameters Section 4.5, “I/O AC Parameters”
2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
Table 48. ECSPI Slave Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
SCLK Cycle Time–Read
SCLK Cycle Time–Write
tclk
15
40
—ns
CS2
SCLK High or Low Time–Read
SCLK High or Low Time–Write
tSW
7
20
—ns
CS4
SSx pulse width
tCSLH
Half SCLK period
—
ns
CS5
SSx Lead Time (CS setup time)
tSCS
5—
ns
CS6
SSx Lag Time (CS hold time)
tHCS
5—
ns
CS7
MOSI Setup Time
tSmosi
4—
ns
CS8
MOSI Hold Time
tHmosi
4—
ns
CS9
MISO Propagation Delay (CLOAD =20pF)
tPDmiso
417
ns
Table 49. Enhanced Serial Audio Interface (ESAI) Timing
No.
Characteristics1’2,3
Symbol
Expression3
Min
Max
Condition4 Unit
62
Clock cycle5
tSSICC
4
× T
c
4
× T
c
30.0
30.0
—
—
i ck
i ck
ns
63
Clock high period
• For internal clock
—2
× T
c − 9.0
6
—
—
ns
• For external clock
—
2
× T
c
15
—
—
Table 47. ECSPI Master Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit



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