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IMX53CEC bảng dữ liệu(PDF) 132 Page - Freescale Semiconductor, Inc |
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IMX53CEC bảng dữ liệu(HTML) 132 Page - Freescale Semiconductor, Inc |
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132 / 204 page ![]() i.MX53xD Applications Processors for Consumer Products, Rev. 2 132 Freescale Semiconductor Electrical Characteristics 4.7.16.4 SSI Receiver Timing with External Clock Figure 84 depicts the SSI receiver external clock timing and Table 86 lists the timing parameters for the receiver timing with the external clock. Figure 84. SSI Receiver External Clock Timing Diagram Table 86. SSI Receiver Timing with External Clock ID Parameter Min Max Unit External Clock Operation SS22 (Tx/Rx) CK clock period 81.4 — ns SS23 (Tx/Rx) CK clock high period 36 — ns SS24 (Tx/Rx) CK clock rise time — 6.0 ns SS25 (Tx/Rx) CK clock low period 36 — ns SS26 (Tx/Rx) CK clock fall time — 6.0 ns SS28 (Rx) CK high to FS (bl) high –10 15.0 ns SS30 (Rx) CK high to FS (bl) low 10 — ns SS32 (Rx) CK high to FS (wl) high –10 15.0 ns SS34 (Rx) CK high to FS (wl) low 10 — ns SS35 (Tx/Rx) External FS rise time — 6.0 ns SS36 (Tx/Rx) External FS fall time — 6.0 ns SS40 SRXD setup time before (Rx) CK low 10 — ns SS41 SRXD hold time after (Rx) CK low 2 — ns SS24 SS34 SS35 SS30 SS28 SS26 SS25 SS23 SS40 SS22 SS32 SS36 SS41 TXC TXFS (bl) TXFS (wl) RXD (Input) |
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