IMX53CEC datasheet(110/204 Pages) FREESCALE

110 / 204 page

i.MX53xD Applications Processors for Consumer Products, Rev. 2

110

Freescale Semiconductor

Electrical Characteristics

4.7.12

PATA Timing Parameters

This section describes the timing parameters of the Parallel ATA module which are compliant with

ATA/ATAPI-6 specification.

Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode

has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA

module interface consist of a total of 29 pins. Some pins act on different function in different transfer

mode. There are different requirements of timing relationships among the function pins conform with

ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.

Table 70 and Figure 63 define the AC characteristics of all the PATA interface signals in all data transfer

modes.

Figure 63. PATA Interface Signals Timing Diagram

The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53xD PATA

interface is 3.3 V compatible.

The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it

difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode

operation is needed, this may not be compatible with bus buffers.

Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.

According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with

a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.

When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a

direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus

should drive from host to device. When its low, the bus should drive from device to host. Steering of the

signal is such that contention on the host and device tri-state busses is always avoided.

Table 70. AC Characteristics of All Interface Signals

Parameter

Symbol

Min

Max

Unit

SI1

Rising edge slew rate for any signal on ATA interface1

1 SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal

amplitude with all capacitive loads from 15

–40 pF where all signals have the same capacitive load value.

Srise

—1.25

V/ns

SI2

Falling edge slew rate for any signal on ATA interface1

Sfall

—1.25

V/ns

SI3

Host interface signal capacitance at the host connector

Chost

—20

ATA Interface Signals

SI1

SI2

IMX53CEC bảng dữ liệu(PDF) 110 Page - Freescale Semiconductor, Inc

IMX53CEC bảng dữ liệu(HTML) 110 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL